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Integrated Circuit Systems, Inc.
ICS9250-23
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset Output Features: * 2 - CPUs @ 2.5V, up to 166MHz. * 13 - SDRAM @ 3.3V, up to 166MHz. * 2 - 3V66 @ 3.3V, 2x PCI MHz. * 8 - PCI @3.3V. * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support power management through PD#. * Spread spectrum for EMI control ( 0.25%) center spread. * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU Output Jitter: <250ps * IOAPIC Output Jitter: <500ps * 48MHz, 3V66, PCI Output Jitter: <500ps * Ref Output Jitter. <1000ps * CPU Output Skew: <175ps * PCI Output Skew: <500ps * 3V66 Output Skew <175ps * For group skew timing, please refer to the Group Timing Relationship Table.
Pin Configuration
56-Pin 300 mil SSOP
1. These pins will have 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2 48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 24MHz
Power Groups GNDREF, VDDREF = REF, Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLKs GNDCOR, VDDCOR = PLLCORE GND48, VDD48 = 48 GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDLPCI, VDDLAPIC = IOAPIC
REF[1:0]
CPU DIVDER
CPUCLK [1:0]
SDRAM DIVDER
SDRAM [11:0] SDRAM_F
FS[4:0] PD#
2
Control Logic Config.
IOAPIC DIVDER
IOAPIC
IC
{
SDATA SCLK
PCI DIVDER
PCICLK [7:0]
Reg.
3V66 DIVDER
3V66 [1:0]
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ICS9250-23
General Description
The ICS9250-23 is a single chip clock solution for desktop designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925023 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN PIN NAME NUMBER 1 REF1 2, 9, 10, 18, 25, 32, 33, 37, VDD 45 3 4 5, 6, 14, 21, 28, 29, 36, 41, 49 8, 7 11 12 X1 X2 GND 3V66 [1:0] PCICLK01 FS0 PCICLK11 FS1 TYPE OUT PWR IN OUT PWR OUT OUT IN OUT IN OUT IN IN I/O OUT IN IN OUT OUT OUT PWR OUT PWR OUT IN OUT DESCRIPTION 3.3V, 14.318MHz reference clock output. 3.3V power supply. Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2. Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) Ground pins for 3.3V supply. 3.3V Fixed 66MHz clock outputs for HUB. 3.3V PCI clock outputs, with Synchronous CPUCLKS. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS. Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Clock input of I2C input. Data pin for I2C circuitry 5V tolerant. 3.3V Fixed 48MHz clock output for USB. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V fixed 24MHz output. 3.3V free r unning 100MHz SDRAM not affected by I2C. 3.3V output r unning 100MHz. All SDRAM outputs can be tur ned off through I2C. Ground for 2.5V power supply for CPU & APIC. 2.5V Host bus clock output. Output frequency der ived from FS p i n s. 2.5V power suypply for CPU, IOAPIC. 2 . 5 V c l o ck o u t p u t s r u n n i n g a t 1 6 . 6 7 M H z . L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V, 14.318MHz reference clock output.
20, 19, 17, 16, PCICLK [7:2] 15, 13 22 23 24 34 35 PD# SCLK SDATA 48MHz FS3 FS2 24MHz
38 SDRAM_F 26, 27, 30, 31, 39, 40, 42, 43, SDRAM [11:0] 44, 46, 47, 48 50 51, 52 53, 55 54 56
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GNDL CPUCLK [1:0] VDDL IOAPIC FS4 REF01
2
ICS9250-23
Frequency Selection
FS4 FS3 FS2 FS1 FS0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU MHz
69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 140.00 133.33 150.00 155.00 166.00 166.00 111.77 104.78 109.51 100.90 117.00 123.75 133.33 142.50 136.00 140.00 143.00 133.90 146.67 149.33 153.30 166.67
SDRAM MHz
103.50 105.00 106.50 100.35 108.00 112.50 114.90 127.50 102.00 111.00 140.00 133.33 150.00 155.00 166.00 166.00 111.77 104.78 109.51 100.90 117.00 123.75 133.33 142.50 102.25 105.00 107.50 100.68 110.00 112.00 115.29 125.32
3V66 MHz
69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 70.00 66.67 75.00 77.50 83.00 111.00 74.52 69.86 73.01 67.27 78.50 82.50 88.89 95.00 68.50 70.00 72.00 67.45 73.33 74.67 77.24 83.34
PCI MHz
34.50 35.00 35.50 33.45 36.00 37.50 38.40 42.50 34.00 37.00 35.00 33.33 37.50 38.75 41.50 55.80 37.26 34.93 36.50 33.63 39.25 41.25 44.44 47.50 34.25 35.00 36.00 33.73 36.67 37.33 38.62 41.67
IOAPIC MHz
17.25 17.50 17.75 16.73 18.00 18.75 19.20 21.25 17.00 18.50 17.50 16.67 18.75 19.38 22.75 27.90 18.63 17.46 18.25 16.82 19.63 20.62 22.22 23.75 17.13 17.50 18.00 16.86 18.33 18.67 19.30 20.83
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OFF ON
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ICS9250-23
Power Down Waveform
Note
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
1.
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ICS9250-23
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used both to provide the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. When no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9250-23
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9250-23
Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable)
Bit Bit (2,7:4) 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit (2, 7:4) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK MHz 69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 140.00 133.33 150.00 155.00 Description SDRAM MHz 103.50 105.00 106.50 100.35 108.00 112.50 114.90 127.50 102.00 111.00 140.00 133.33 150.00 155.00 3V66 MHz 69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 70.00 66.67 75.00 77.50 PCICLK 34.50 35.00 35.50 33.45 36.00 37.50 38.40 42.50 34.00 37.00 35.00 33.33 37.50 38.75 41.50 55.80 37.26 34.93 36.50 33.63 39.25 41.25 44.44 47.50 34.25 35.00 36.00 33.73 36.67 37.33 38.62 41.67 IOAPIC MHz 17.25 17.50 17.75 16.73 18.00 18.75 19.20 21.25 17.00 18.50 17.50 16.67 18.75 19.38 22.75 27.90 18.63 17.46 18.25 16.82 19.63 20.62 22.22 23.75 17.13 17.50 18.00 16.86 18.33 18.67 19.30 20.83 0 1 0 PWD
00100 Note 1
Bit 3 Bit 1 Bit 0
0 1 1 1 0 166.00 166.00 83.00 0 1 1 1 1 166.00 166.00 111.00 1 0 0 0 0 111.77 111.77 74.52 1 0 0 0 1 104.78 104.78 69.86 1 0 0 1 0 109.51 109.51 73.01 1 0 0 1 1 100.90 100.90 67.27 1 0 1 0 0 117.00 117.00 78.50 1 0 1 0 1 123.75 123.75 82.50 1 0 1 1 0 133.33 133.33 88.89 1 0 1 1 1 142.50 142.50 95.00 1 1 0 0 0 136.00 102.25 68.50 1 1 0 0 1 140.00 105.00 70.00 1 1 0 1 0 143.00 107.50 72.00 1 1 0 1 1 133.90 100.68 67.45 1 1 1 0 0 146.67 110.00 73.33 1 1 1 0 1 149.33 112.00 74.67 1 1 1 1 0 153.30 115.29 77.24 1 1 1 1 1 166.67 125.32 83.34 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread spectrum enable 0.25% Center Spread 0- Running 1- Tristate all outputs
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
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ICS9250-23
Byte 1: Control Register (1 = enable, 0 = disable)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 35 34 38
PWD 0 0 0 1 1 1 1 1
Description FS3# FS0# FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 39 40 42 43 44 46 47 48
PWD 1 1 1 1 1
1
1 1
Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: Control Register (1 = enable, 0 = disable)
Byte 4: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 17 16 15 13 12 11
PWD 1 1 1 1 1
1
1 1
Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 7 8 54 51 52
PWD 1 1 1 0 1 0 1 1
Description (Reserved) 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0
Byte 5: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 26 27 30 31
PWD 1 1 1 1 1 1 1 1
Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
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ICS9250-23
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table
Group CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI USB & DOT CPU 66MHz Offset 2.5ns 7.5ns 0.0ns 1.5-3.5ns Asynch Tolerance 500ps 500ps 500ps 500ps N/A CPU 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns Asynch Tolerance 500ps 500ps 500ps 500ps N/A CPU 133MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns Asynch Tolerance 500ps 500ps 500ps 500ps N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Current Input frequency Input Capacitance1 Transition Time1 Settling Time
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 I DD3.3V I DDL2.5V IDD3.3VPD Fi CIN CINX TTrans TS TStab TPZH,TPZL TPHZ, TPLZ
MIN TYP MAX UNITS 2 VDD + 0.3 V VSS - 0.3 0.8 V VIN = VDD -5 5 mA VIN = 0 V; Inputs with no pull-up resistors -5 mA VIN = 0 V; Inputs with pull-up resistors -200 mA Cl = 0 pF; Select @ 66M 119 280 mA Cl = 0 pF; Select @ 66M 3 25 Cl = 0 pF; With Input to Vdd or Gnd 600 mA VDD = 3.3 V 14.318 MHz Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay(all outputs) output disable delay(all outputs) 1 1 1 27 5 45 3 3 3 10 10 pF pF ms ms ms ns ns
CONDITIONS
Clk Stabilization Delay 1
1
Guaranteed by design, not 100% tested in production.
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ICS9250-23
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-Cycle Jitter, Cycle-to-Cycle
1
SYMBOL CONDITIONS VOH2B IOH = -1 mA VOL2B IOL = 1 mA VOH@MIN = 1 V IOH2B VOH@MAX = 2.375V VOL@MIN = 1.2 V IOL2B VOL@MAX =0.3V tr2B1 tf2B1 dt2B1 t sk2B1 t jcyc-cyc2B tjcyc-cyc 1
1
MIN 2
-27 27 0.4 0.4 45
TYP 2.45 0.05 -52.6 -6.5 38.6 11.6 1.12 1.16 48 78 180 120
MAX UNITS V 0.4 V -27 mA mA ns ns % ps ps ps
30 1.6 1.6 55 175 300 250
VOL = 1 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V (CPU 133, SDRAM 100) VT = 1.25 V (all other select B)
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Jitter,
1 1 1
SYMBOL CONDITIONS I OH = -18 mA VOH4B I OL = 9 mA VOL4B VOH = 2.0 V IOH4B VOL@MIN = 1.0 V IOL4B VOL@MAX =0.2V Tr4B Tf4B Dt4B tjcyc-cyc4B1 VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 2.4
31 0.4 0.4 45
TYP 2.9 0.25 -58 34.1 7.85 1.28 1.2 49.6 432
MAX UNITS V 0.4 V -22 mA 31 2 1.6 55 750 mA ns ns % ps
Duty Cycle
Cycle-to-Cycle
Guaranteed by design, not 100% tested in production.
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ICS9250-23
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PC PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1 1
SYMBOL CONDITIONS VOH1 IOH = -1 mA VOL1 IOL = 1 mA VOH@MIN = 1 V IOH1 VOH@MAX = 3.135V VOL@MIN = 1.95 V I OL1 VOL@MAX =0.4V t r1 t f1 dt1 t sk1 tjcyc-cyc1 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
-33 38 0.5 0.5 45
TYP 3.25 0.03 -71 -10 74 22 1.65 1.53 51.1 331 185
MAX UNITS V 0.55 V -33 mA mA ns ns % ps ps
30 2 2 55 500 500
Duty Cycle
Skew Jitter, Cycle-to-Cycle
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew1 Jitter1,Cycle-to-Cycle
1 1 1
SYMBOL CONDITIONS VOH1 IOH = -1 mA IOL = 1 mA VOL1 VOH@MIN = 1 V IOH1 VOH@MAX = 3.135V VOL@MIN = 1.95 V I OL1 VOL@MAX =0.4V t r1 VOL = 0.4 V, VOH = 2.4 V t f1 dt1 t sk1 tjcyc-cyc1 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
-38 30 0.4 0.4 45
TYP 3.25 0.05 -94.6 -11.9 87.5 27.1 0.86 0.77 48.2 121 294
MAX UNITS V 0.55 V -38 mA mA ns ns % ps ps
38 1.6 1.6 55 175 500
Duty Cycle
Guaranteed by design, not 100% tested in production.
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ICS9250-23
Electrical Characteristics - 24MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Jitter
1 1 1 1
SYMBOL CONDITIONS IOH = -1 mA VOH5 IOL = 1 mA VOL5 VOH@MIN = 1 V IOH5 VOH@MAX = 3.135V VOL@MIN = 1.95 V I OL5 VOL@MAX =0.4V t r5 t f5 dt5 tjcyc-cyc5 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, 24MHz
MIN 2.4
-23 29
TYP 3.25 0.05 -35.2 -4.9 37.8 11.6 2.32 2.29
MAX UNITS V 0.4 V -27 mA mA ns ns % ps
27 4 4 55 1400
Duty Cycle
45
49.6 615
,Cycle-to-Cycle
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, REF
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL CONDITIONS VOH5 IOH = -1 mA VOL5 IOL = 1 mA VOH@MIN = 1 V IOH5 VOH@MAX = 3.135V VOL@MIN = 1.95 V I OL5 VOL@MAX =0.4V t r5 t f5 dt5 tjcyc-cyc5 tjcyc-cyc5 tjcyc-cyc5 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, 24MHz VT = 1.5 V, 48MHz VT = 1.5 V, REF
MIN 2.4
-33 38
TYP 3.25 0.05 -68.5 -8.9 72.3 22 1.67 1.68
MAX UNITS V 0.4 V -27 mA mA ns ns % ps ps ps
30 4 4 55 1400 750 1550
Duty Cycle
45
52 615 522 465
Jitter1, Cycle-to-Cycle Jitter1, Cycle-to-Cycle Jitter1, Cycle-to-Cycle
1
Guaranteed by design, not 100% tested in production.
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ICS9250-23
Electrical Characteristics - SDRAM
TA = 0 - 70C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle
1
SYMBOL CONDITIONS I OH = -1 mA V OH1 V OL1 I OL = 1 mA VOH@MIN = 2 V I OH1 V OH@MAX = 3.135V VOL@MIN = 1 V I OL1 V OL@MAX =0.4V t r1 t f1 dt1 t sk1 t jcyc-cyc1 V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
MIN 2.4
-46 54 0.4 0.4 45
TYP 3.28 0.03 -85 -12 63 27 1.25 1.53 53.2 267 176
MAX UNITS V 0.4 V -54 mA mA ns ns % ps ps
53 1.6 1.6 55 380 250
Skew Jitter1, Cycle-to-Cycle
1
Guaranteed by design, not 100% tested in production.
(No Skew Window is needed for Group Skew spec.) TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% 24MHz, 48MHz, REF, CPU & IOAPIC load = 20 pF; PCI, SDRAM & 3V66 load = 30 pF. Refer to Group Offset Waveform diagram for definition of transition edges.
Group Skews (CPU = 66 MHz; SDRAM = 100MHz)
PARAMETER CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI Skew Skew1 Skew1 Skew1
1
SYMBOL Tsk1 CPU-SDRAM Tsk1 CPU-3V66 Tsk1 SDRAM-3V66 Tsk1 3V66-PCI
CONDITIONS CPU @ 1.25 V, SDRAM @ 1.5 V CPU @ 1.25 V, 3V66 @ 1.5 V SDRAM @1.5V, 3V66 @ 1.5 V 3V66 @1.5V, PCI @ 1.5 V
MIN 2.0 7 -500 1.5
TYP
394 2.58
MAX UNITS 3.0 ns 8 ns 500 ps 3.5 ns
Group Skews (CPU = 100 MHz; SDRAM = 100MHz)
PARAMETER CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI Skew Skew1 Skew1 Skew1
1
SYMBOL Tsk1 CPU-SDRAM Tsk1 CPU-3V66 Tsk1 SDRAM-3V66 Tsk1 3V66-PCI
CONDITIONS CPU @ 1.25 V, SDRAM @ 1.5 V CPU @ 1.25 V, 3V66 @ 1.5 V SDRAM @1.5V, 3V66 @ 1.5 V 3V66 @1.5V, PCI @ 1.5 V
MIN 4.5 4.5 -500 1.5
TYP 4.63 396 2.58
MAX UNITS 5.5 ns 5.5 ns 500 ps 3.5 ns
Group Skews (CPU = 133 MHz; SDRAM = 100MHz)
PARAMETER CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI
0391B--09/18/03
Skew1 Skew1 Skew1 Skew1
SYMBOL Tsk1 CPU-SDRAM Tsk1 CPU-3V66 Tsk1 SDRAM-3V66 Tsk1 3V66-PCI
CONDITIONS CPU @ 1.25 V, SDRAM @ 1.5 V CPU @ 1.25 V, 3V66 @ 1.5 V SDRAM @1.5V, 3V66 @ 1.5 V 3V66 @1.5V, PCI @ 1.5 V
MIN -500 -500 -500 1.5
TYP -322 -284 389 2.61
MAX UNITS 500 ps 500 ps 500 ps 3.5 ns
13
ICS9250-23
0ns
25ns
50ns
75ns
CPU 66 Period
CPU/ITP/HCLK [66MHz (2.5V)]
CPU 100 Period
CPU/ITP/HCLK [100MHz (2.5V)]
SDRAM 100 Period
SDRAM [11:0, F] & DCLKWR [100MHz (3.3V)]
3V66-PCI
3V66 Link (ICH / MGCH) [66MHz (3.3V)] PCI [7:0] LPC/SIO [33MHz (3.3V)] Ref Clock [14.318MHz (3.3V)] USB [48MHz (3.3V)] APIC (CPU/MCH) [16.67MHz (2.5V)]
Group Offset Waveforms
0391B--09/18/03
14
ICS9250-23
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9250yF-23
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator
Device Type Prefix ICS, AV = Standard Device
0391B--09/18/03
15

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